Exemplary embodiments relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a non-volatile memory device having a three-dimensional (3-D) structure and a method of manufacturing the same.
Nonvolatile memory devices retain stored data even when power is interrupted. Two-dimensional (2D) memory devices fabricated in a single layer on a silicon substrate have limitations in improving integration density. Therefore, 3D nonvolatile memory devices with memory cells stacked vertically from a silicon substrate have been proposed.
The structure of a conventional non-volatile memory device having a 3-D structure and features thereof are described below with reference to relevant drawings.
FIGS. 1A and 1B are layout diagrams of a conventional U-shaped channel type non-volatile memory device.
As shown, the conventional U-shaped channel type non-volatile memory device includes a plurality of drain-side word lines D_WL and a plurality of source-side word lines S_WL, which are extended in parallel in a first direction I-I′. The plurality of drain-side word lines D_WL and the plurality of source-side word lines S_WL are alternately arranged.
The plurality of drain-side word lines D_WL and the plurality of source-side word lines S_WL are arranged in a stack form. A plurality of the drain-side word lines D_WL formed in the same level are interconnected, and a plurality of the source-side word lines S_WL formed in the same level are also interconnected.
The non-volatile memory device further includes a plurality of source lines SL extended in parallel in the first direction I-I′ on the source-side word lines S_WL.
The non-volatile memory device further includes a plurality of strings S0 to S3 arranged in the first direction I-I′ and a second direction II-II′ and a plurality of bit lines BL arranged in parallel in the second direction II-II′. The strings S0 to S3 arranged in the second direction II-II′ are coupled to the same bit line BL. In the drawings, drain contact plugs are indicated by symbols {circle around (×)}, and source contact plugs are indicated by symbols ◯.
FIG. 2 is a perspective view illustrating the structure of the conventional non-volatile memory device having a 3-D structure. Interlayer dielectric layers are not shown in FIG. 2, for illustration purposes.
As shown, the conventional U-shaped channel type non-volatile memory device includes a plurality of U-shaped channels CH arranged in a first direction I-I′ and a second direction II-II′ crossing the first direction I-I′. Each of the U-shaped channels CH includes a first channel CH1 and a pair of second channels CH2 coupled to the first channel CH1.
The non-volatile memory device further includes a plurality of memory cells MC stacked along the U-shaped channel CH. A drain select transistor DST and a source select transistor SST are provided at both ends of the U-shaped channel CH. A plurality of the memory cells MC arranged between the drain select transistor DST and the source select transistor SST form one string S1 or S0. The non-volatile memory device further includes a bit line BL0 coupled to the channel of the drain select transistor DST and a source line SL coupled to the channel of the source select transistor SST.
Each of the memory cells MC includes the second channel CH2, a tunnel insulating layer (not shown), a charge trap layer (not shown), and a charge blocking layer (not shown) surrounding the second channel CH2, and a word line WL. The drain select transistor DST includes the second channel CH2, a gate insulating layer (not shown) surrounding the second channel CH2, and a drain select line DSL0 or DSL1. The source select transistor SST includes the second channel CH2, a gate insulating layer (not shown) surrounding the second channel CH2, and a source select line SSL.
FIG. 3A is a circuit diagram illustrating part of the cell array of the conventional non-volatile memory device having a 3-D structure. The cell array of FIG. 3A illustrates the cell array of strings S0 to S3 included in one of the string columns and coupled to the bit line BL0 of FIGS. 1A and 1B.
As shown, the strings S0 to S3 are coupled to the same bit line BL0. The strings S0 to S3 include respective drain select lines DSL0 to DSL3 and respective source select lines SSL0 to SSL3 that drive the strings S0 to S3.
In this structure, memory cells formed in the same level and formed to share a source-side word line or a drain-side word line must be driven as different pages because they are coupled to the same bit line BL0. For example, when the source-side word lines WL14 are driven, the memory cells are driven as four pages page_n to page_n+3, respectively, by controlling the drain select lines DSL0 to DSL3 and the source select lines SSL0 to SSL3.
FIG. 3B is a diagram illustrating the page numbers of the conventional non-volatile memory device having a 3-D structure. The page numbers of FIG. 3B show the page numbers of the cell array shown in FIG. 3A.
For example, in a device that includes 32 memory cells in one string that are driven as Multi-Level Cells (MLCs), memory cells included in four strings are driven as a total of 256 (4*32*2) pages.
The conventional non-volatile memory device having a 3-D structure has the following features.
First, packaging is difficult. The size of a page (more specifically, the number of memory cells included in one page) is increasing. In the conventional structure, the X axis of a chip must be greatly increased to increase the size of the page. Accordingly, a standard package size cannot be implemented.
Second, a conventional controller and application products cannot be used. The number of pages included in one memory block of the conventional non-volatile memory device having a 3-D structure is greater than that of a non-volatile memory device having a 2-D structure because strings included in one string column are driven as respective pages. For example, if the conventional non-volatile memory device having a 3-D structure includes four strings each including 32 memory cells that are driven as an MLC, the memory cells are driven as a total of 256 pages. Accordingly, a new controller and application products are to be developed.
Third, as the number of pages included in one memory block increases, interference between memory cells is increased, and a distribution of the threshold voltages of programmed memory cells is deteriorated.
Fourth, an increase in the degree of integration of the non-volatile memory devices having a 3-D structure is reaching a limit. In the conventional structure, a reduction in the line width is limited because the diameter of a channel, and the thickness of a tunnel insulating layer, a charge trap layer, and a charge blocking layer, and an interval between strings must be secured. In order to improve the degree of integration, the number of memory cells stacked must be increased. If the number of memory cells stacked increases, however, the process that forms the conventional non-volatile memory devices having a 3-D structure may become more difficult.